module par_ser_rtl (sh_clk, rst, load, par_in, ser_out);
   input       sh_clk;  // shift clock
   input       rst;     // reset signal
   input       load;    // load enable
   input [7:0] par_in;  // parallel input
   output      ser_out; // serial output

   reg [7:0] par_reg;
   reg [2:0] iterat;
   reg       done;

always @(posedge sh_clk, posedge rst) begin
if (rst)
   begin
      par_reg <= 8'h00;
      iterat <= 3'b000;
      done <= 1'b1;
   end
else
   if (done)
      begin
         if (load)
            begin
               par_reg <= par_in;
               iterat <= 3'b000;
               done <= 1'b0;
            end
      end
   else
      begin
         par_reg <= {1'b0, par_reg[7:1]};
         iterat <= iterat + 1'b1;
         if (iterat == 3'b111)
            done <= 1'b1;
      end
end

assign ser_out = par_reg[0];

endmodule